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Integrated Linear DDR Termination Regulator
POWER MANAGEMENT Description
The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination. The SC2595 can source and sink 1.5A current at the output VTT while maintaining excellent load regulation. VTT is designed to track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through on the output stage. A VSENSE pin is incorporated to provide excellent load regulation, along with a buffered reference voltage. The SC2595 incorporates a disable function built into the AVCC pin to tri-state the output during Suspend To Ram (STR) states. (Multiple patents pending.)
SC2595
Features
Regulates while sourcing or sinking 1.5A AVCC range is from 2.5V to 5V Reference output Minimum number of external components Accurate internal voltage divider SOIC-8L EDP package. Also available in Lead-free package, fully WEEE and RoHS compliant
Applications
DDR memory termination High speed data line termination PC motherboards Graphics boards Disk drives CD-ROM drives
Typical Application Circuit
VDD
SC2595
1 2 3 VREF 4 NC GND VSENSE VREF VTT PVCC AVCC VDDQ 8 7 6 5 VTT
Revision: June 12, 2007
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SC2595
POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
P ar am et er PVCC, AVCC, VDDQ to GN D Thermal Resistance Junction to Case SOIC-8L EDP Thermal Resistance Junction to Ambient SOIC-8L EDP Op erating Temp erature Range Op erating Junction Temp erature Range Storage Temp erature Range Peak IR Reflow Temp erature 10 - 40s Peak IR Reflow Temp erature 10 - 40s ESD Rating (Human Body Model)
S y m b ol VCC JC JA TA TJ TSTG T LE A D T LE A D ESD
M ax i m u m -0.3 to +6.0 5.5
Units V C/W
36.5 -40 to +105 -40 to +150 -65 to +150 240 260 2
C/W C C C C C KV
Operating Range
P ar am et er Junction Temp erature Range AVCC to GN D PVCC to GN D S y m b ol TJ AVCC PVCC M ax i m u m -40 to +150 2.3 to 5.5 2.3 to AVCC Units C V V
Electrical Characteristics
Specifications with standard typeface are for TJ = 25oC and limits in boldface type apply over the full Operating Temperature Range (TJ = -40oC to +150oC). Unless otherwise specified, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
P ar am et er Reference Voltage Load Regulation
(1)
S y m b ol V REF REGLOAD V OSV TT IQ
Te s t C o n d i t i o n s IREF_OUT = 0mA ILOAD : 0 to +1.5A ILOAD : 0 to -1.5A IOUT=0A , V TT- V REF ILOAD = 0A
Min V DDQ/2 - 40mV
Ty p 1.25 -0.5 +0.5
M ax V DDQ/2 + 40mV
Units V %
V TT Outp ut Voltage Offset Quiescent Current AV CC Enab le Threshold V DDQ Inp ut Imp edance
-20
0 400 2.1
+20
mV A V k
ZVDDQ
100
Note: (1) For Load Regulation, use a 10ms current pulse width when measuring VTT.
(c) 2007 Semtech Corp.
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SC2595
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Par t Number SC2595STRT(1)(2) SC2595EVB Package SOIC-8L EDP Temp. Range (T A ) -40 to +105OC
Evaluation Board
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for SOIC-8L package. (2) Lead free package. Device is fully WEEE and RoHS compliant.
(SOIC-8L EDP)
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SC2595
POWER MANAGEMENT Pin Descriptions
S O I C- 8L E DP Pin # 1 2 3 P i n N am e NC GN D V SEN SE N o internal connection. Ground. V SENSE is a feedb ack p in. V TT p lane is always a narrow and long strip p lane in most m o t h e r b o ar d ap p l i cat i o n s. T h i s l o n g st r i p p l an e w i l l cau se a l ar g e t r ace inductance and trace resistance. Consider the load transient condition; a fast load current going through V TT strip p lane can create voltage sp ikes on the V TT p lane. The load current can also cause a DC voltage drop on the V TT p lane. It is recommen d ed th at V SEN SE sh ou l d b e con n ected to th e cen ter of V TT p l an e to i mp rove th e l oad regu l ati on an d th e n oi se i mmu n i ty. In case th at on e can 't connect the V SENSE p in to the center of the V TT p lane, one should connect it to the SC2595 V TT p in directly. A longer trace of V SENSE may p ick up noise and cause the error of load regulation; hence the longer trace must b e avoided. A 10nF to 100nF ceramic cap acitor close to the V SENSE p in is req uired to avoid oscillation during transient condition. V REF is an outp ut p in, which p rovides the b uffered outp ut of the internal reference voltage. System designer can use the V REF outp ut voltage for N or thb ridge chip set an d memory. B ecau se th ese i n p u t p i n s are ty p i cal l y h i gh i mp ed an ce, th ere should b e a small amount of current drawn from the VREF p in [figure 9, 10]. To imp rove the noise immunity, a ceramic cap acitor (10nF - 100nF) should b e added from the V REF p in to ground with shor t distance. The V DDQ p in is an inp ut for creating internal reference voltage to regulate V TT. The V DDQ voltage is connected to internal 100Kohm resistor divider. The central tap of resi stor d i vi d er ( V DDQ/2) i s con n ected to th e i n tern al vol tage b u ffer, w h i ch outp ut is connected to V REF p in and the non-inver ting inp ut of the error amp lifier as the reference voltage. With the feedb ack loop closed, the V TT outp ut voltage will always track the V DDQ/2 p recisely. It is recommended to use 5.1 ohm + a 1uF ceramic cap acitor for V DDQ p in's filter to increase the noise immunity. The AV CC p in is used to sup p ly all of the internal control circuitry. AV CC voltage h as to b e greater th an i ts U V LO th resh ol d vol tage ( 2.1V ty p i cal ) to al l ow th e SC2595 b e in normal op eration. If AV CC voltage is lower than the UV LO threshold voltage, the V TT outp ut voltage will remain at 0V. The PV CC p in p rovides the rail voltage from where the V TT p in draws load current. There is a limitation b etween AV CC and PV CC. The PV CC voltage must b e less or eq ual to AV CC voltage to ensure the correct outp ut voltage regulation. The V TT source current cap ab ility is dep endent on PV CC voltage. Higher the voltage on PV CC, higher the source current; however, it will cause more p ower loss and higher temp erature rise [figure 5, 11, 12]. The V TT p in is the outp ut of SC2595. It can sink and source 1.5A continuous cu rren t an d 3A p eak cu rren t w h i l e k eep i n g ex cel l en t l oad reg u l at i on . I t i s recommen d ed th at on e sh ou l d u se at l east 220u F l ow E SR cap aci tors ( E SR sh ou l d b e l ow er t h an 250m oh m) an d 10u F cerami c cap aci t ors, w h i ch are uniformly sp read on the VTT strip p lane to reduce the voltage sp ike under load transient condition. Thermal p ad should b e connected to GN D.
(1)
PRELIMINARY
P i n Fu n c t i o n
4
V REF
5
V DDQ(2)
6
AV CC (2)
7
PV CC (2)
8
V TT
Thermal Pad
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SC2595
POWER MANAGEMENT
Notes: (1) Can be used for vias. (2) Power up of AVCC, PVCC and VDDQ supplies. (a) The preferred mode of operation is when the AVCC, PVCC and VDDQ pins are tied together to a single supply. (b) If and when AVCC, PVCC pins are tied to a supply separate to that of the VDDQ supply pin; then the VDDQ supply should lead AVCC, PVCC supply or the VDDQ supply and the AVCC, PVCC supply should rise simultaneously. (c) If the AVCC, PVCC and VDDQ supply pins are connected in a way such that, AVCC, PVCC supplies precedes VDDQ supply; then VTT output precedes VDDQ. This can cause the SDRAM device to latch-up, which may cause permanent damage to the SDRAM.
Block Diagram
AVCC UVLO VDDQ
PVCC
OUT
+
OUT
+ -
Driver Circuit
VTT
VREF
GND
VSENSE NC
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SC2595
POWER MANAGEMENT Application Information
Overview Double Data Rate (DDR) SDRAM was defined by JEDEC 1997. Its clock speed is the same as previous SDRAM but data transfers speed is twice than previous SDRAM. By now, the requirement voltage range is changed from 3.3V to 2.5V; the power dissipation is smaller than SDRAM. For above reasons, it is very popular and widely used in M/B, N/B, Video-cards, CD ROM drives, Disk drives. Regarding the DDR power management solution, there are two topologies can be selected for system designers. One is switching mode regulator that has bigger sink/ source current capability, but the cost is higher and the board space needed is bigger. Another solution is linear mode regulator, which costs less, and needs the less board space. For two DIMM motherboards, system designers usually choose the linear mode for DDR power management solution. Applications Circuits Wa eforms Typical Application Cir cuits & W a v ef orms Two different application circuits are shown below in Figure 1 to Figure 2. Each circuit is designed for specific condition. More details are described below. See Note 1. Below for recommended power up sequencing. Standard SSTL TL-2 Application_1: Standar d SS TL-2 Application The AVCC pins, the PVCC pin, and the VDDQ pin can be tied together for SSTL-2 application. It only needs a 2.5V power rail for normal operation. System designer can save the PCB space and reduce the cost. Please refer to figures 3 to 4 for test waveforms.
SC2595
1 2 3 4 NC GND VSENSE VREF VTT PVCC AVCC VDDQ 8 7 6 5 R1 5.1 Cin1 68uF Cin2 1uF VDD 2.5V Cout1 Cout2 220uF 10uF VTT 1.25V
PRELIMINARY
Application_2: Lower Power Loss Configuration SSTL TL-2 f or SS TL-2 If power loss is a major concern, separated the PVCC form the AVCC and the VDDQ will be a good choice. The PVCC can operate at lower voltage (1.8V to 2.5V). If 2.5V voltage is applied on AVCC and the VDDQ, but the source current is lower due to the lower operating voltage applied on the PVCC. Please find the relative test result in Figures 5, 11 and 12.
SC2595
1 2 3 4 Csense 2.2uF NC GND VSENSE VREF VTT PVCC AVCC VDDQ 8 7 6 5 R2 R
1.8V to 2.5V 2.5V VDD Vin Cin1
68uF
VTT
1.25V
Cin2
1uF
Cout1
220uF
Cin2
10uF
Cref
10nF
Cddq
1uF
Figure 2: Lower power loss for SSTL-2 application
Notes:
(1) Power up of AVCC, PVCC and VDDQ supplies. (a) The preferred mode of operation is when the AVCC, PVCC and VDDQ pins are tied together to a single supply. (b) If and when AVCC, PVCC pins are tied to a supply separate to that of the VDDQ supply pin; then the VDDQ supply should lead AVCC, PVCC supply or the VDDQ supply and the AVCC, PVCC supply should rise simultaneously. (c) If the AVCC, PVCC and VDDQ supply pins are con nected in a way such that, AVCC, PVCC supplies precedes VDDQ supply; then VTT output precedes VDDQ. This can cause the SDRAM device to latchup, which may cause permanent damage to the SDRAM.
Csence Cref 2.2uF 10nF
Figure 1: Standard SSTL-2 application
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SC2595
POWER MANAGEMENT Application Information (Cont.)
Layout guidelines 1)The SC2595 has a power SO-8 package. It can improve the thermal impedance (JC) significantly. A suitable thermal pad should be added when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB ground layer. This will improve the thermal performance . 2)To increase the noise immunity, a ceramic capacitor of 10nf to 100nf is required to decouple the VREF pin with the shortest connection trace, also A 10nF to 100nF ceramic capacitor close to the VSENSE pin is required to avoid oscillation during transient condition. 3)To reduce the noise on the input power rail for standard SSTL-2 application, a 68F low ESR capacitor and a 1F ceramic capacitor have to be used on the input power rail with shortest possible connection. 4)For lower power loss SSTL-2 application, a 220F AL. capacitor (ESR should be lower than 250m ohm) and a 10F ceramic has to be added on the PVCC pin and a 1F ceramic capacitor +5.1 ohm filter has to be added on the VDDQ pin with shortest possible connection. 5)VTT output copper plane should be as large as possible. 6)VSENSE trace should be as short as possible.
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SC2595
POWER MANAGEMENT Test Waveforms
Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V Cout1=220uF, Cout2=10uF, Source 2A.
PRELIMINARY
Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V Cout1=220uF, Cout2=10uF, Sink 2A.
VDDQ AVcc PVcc
VDDQ AVcc PVcc
VTT
VTT
VREF
VREF
Figure 3
Figure 4
Typical Characteristics
AVCC=VDDQ=2.5V
3.00 2.75 2.50
AVcc vs IQ
600 550 500 450 Quiescent current(uA) 400 350 300 250 200 150 100 VDDQ =2.5V VDDQ =1.8V
OUTPUT CURRENT(A)
2.25 2.00 1.75 1.50 1.25 1.00 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 PVCC(V)
MAX SOURCE CURRENT
50 0 2.5
3.0
3.5
4.0 4.5 AVcc(V)
5.0
5.5
6.0
Figure 5
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SC2595
POWER MANAGEMENT Typical Characteristics (Cont.)
Quiescent Current(AVCC= 2.5V)
800
2.00 1.99
Temp vs UVLO
700
1.98 1.97 Voltage(V)
600 Current(uA) 2.5V 500 1.8V
1.96 1.95 1.94 1.93
UVLO (Ty pical)
400
300
1.92 1.91
200 0 20 40 60 80 100 120 140 Temperature ()
1.90 20 30 40 50 60 70 80 90 100 110 Temperature()
Figure 7
Figure 8
VDDQ=PVCC=AVCC=2.5V
1.250 1.245 1.240 1.235 VREF(V)
1.250 1.245 1.240 1.235
VREF_max vs IREF(VDDQ=2.5V)
-40 0 25 75
VREF(V)
1.230 1.225 1.220 1.215 1.210 0 100 200 300 400 500 600 700 800 900 IREF(uA)
1.230 1.225 1.220 1.215 1.210 0 100 200 300 400 500 600 700 800 900
150
IREF(uA)
Figure 9
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Figure 10
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SC2595
POWER MANAGEMENT Typical Characteristics (Cont.)
VDDQ=2.5V
6.5 6.0 5.5 5.0 Current(A) 4.5 4.0 3.5 3.0 2.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVCC=PVCC(V)
Current(A)
PRELIMINARY
VDDQ=1.8V
6.0 5.5 5.0 4.5
MAX SOURCE CURRENT
4.0 3.5 3.0 2.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
AVCC=PVCC(V)
MAX SOURCE CURRENT
Figure 11
AVCC=PVCC=VDDQ=2.5V
140
Figure 12
120
100 Temperature( )
80 SOURCE 60 SINK
40
20
0 0.0
0.5
1.0
1.5
2.0
2.5
DC CURRENT (A)
Figure 13
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SC2595
POWER MANAGEMENT Outline Drawing - Power SOIC-8L
A e N D
DIM
2X E/2 E1 E
A A1 A2 b c D E1 E e F h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .005 .000 .065 .049 .012 .020 .010 .007 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .086 .090 .094 .010 .020 .016 .028 .041 (.041) 8 0 8 .004 .010 .008 1.75 1.35 0.13 0.00 1.65 1.25 0.31 0.51 0.25 0.17 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 2.19 2.29 2.39 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0 8 0.10 0.25 0.20
1 ccc C 2X N/2 TIPS
2 e/2 B D
aaa C A2 A SEATING PLANE C bxN bbb F EXPOSED PAD A1 C A-B D
h
h H F GAGE PLANE 0.25 L (L1) DETAIL SEE DETAIL SIDE VIEW
NOTES: 1. 2. 3. 4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
c
01
A
A
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS-012, VARIATION BA.
Land Pattern - Power SOIC-8L
E D SOLDER MASK
DIM
(C) F G Z C D E F G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .098 .201 .096 .118 .050 .024 .087 .291 (5.20) 2.49 5.10 2.44 3.00 1.27 0.60 2.20 7.40
Y THERMAL VIA ? 0.36mm P X
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
2. 3.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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